A 19-level switched-capacitor inverter topology is presented in this paper with the objectives of reducing the number of components, achieving high voltage gain, and minimizing voltage ripple. The proposed structure consists of 12 switches, six capacitors, and six diodes. Due to the low voltage stress on the devices, the reduced number of power switches, and the use of diodes, the overall cost of the inverter is decreased. The capacitor cost is a function of both the rated voltage and the capacitance. In the proposed topology, the rated voltage of capacitors is relatively low owing to the appropriate arrangement of switched-capacitor units. Also, the proposed inverter supports redundant switching states (RSS) for charging all the switched-capacitor units. These states, combined with the proposed hybrid pulse-width modulation (HPWM) technique, minimize the longest continuous discharging period (LDP) of the capacitors. The accelerated completion of continuous capacitor discharging and subsequent recharging at more voltage levels contributes to a significant reduction in both voltage ripple and inrush current, and the capacitor size . The proposed structure is thoroughly analyzed, including circuit description, the proposed modulation method, capacitor sizing, and power loss evaluation. Moreover, the inverter is compared with similar structures in terms of both qualitative and quantitative aspects. For a more comprehensive assessment, a cost comparison based on the actual device cost is also provided. Finally, the proposed inverter has been experimentally implemented in the laboratory, and both steady-state and dynamic performance have been investigated. The corresponding experimental results are presented to validate the analysis.